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FEATURES
* IEEE802.3 Clause 9 and IEEE802.3u Cluse 27 compliant. * Provide 8 RMII (8 port mode), or 4 RMII + 1 MII (5 port mode). * Provide 2 inter_repeater stacking bus for 10M and 100M port expansion each. * Support stacking to 4 units without any external arbitration logic ( if use external arbitration logic, theoretically can stack to 6 units and up) . * Build_in 2 port switch controller, support up to 2048 MAC addresses filtering database. * Optional back_pressure flow control. * Optional up_link_switch port function (in slave hub), support 100FX 2km distance extension in 100FD mode. * Meet Class_2 repeater specification for 100M_hub. * Pin compatible with MTD658/655 application, no need any external memory buffers. * 128 pin QFP package, 3.3V operation voltage.
MTD658E
5/8 Port 10/100 Hub Build_in Bridge And Memory
GENERAL DESCRIPTION
The MTD658E is a highly integrated, 10M/ 100M dual speed hub with build_in 2 port switch and 64k8 embedded ASRAM. Support 8 RMII ports for 10M/100M operation, and really meet 100M_hub class_2 spec when connect with external QPHYceivers. The MTD658E provides two Inter-repeater stacking bus for 10M and 100M expansion each, easily stack to 4 units without any external arbitration logic. If using external arbitration logic and proper bus driver, can stack to 6 units and up. The build_in 2 port switch, support 2k MAC addresses filtering, and use embedded asynchronous high speed SRAM (64k*8) for packet buffering. This 2 port switch can also be configured to be up_link switch when hub is under slave mode. The MTD658E also support an simple and effective LED display function, provide 10M_col, 100M_col, and per port' partition status. s
BLOCK DIAGRAM
Two Port Switch Embedded 64k8 ASRAM
Uplink Switch Enable(10/100,FD/HD)
RMII7
10M_HD 10M Inter Hub Bus
RMII6 RMII5 RMII4 RMII3 RMII2 RMII1 RMII0
10M Hub
Port Switch Logic
100M_HD 100M Inter Hub Bus
100M Hub
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. 1/23 MTD658E Revision 1.1 05/25/2000
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SYSTEM DIAGRAM
MTD658E
DB25 Connector
10M Inter Hub Bus
MTD658E
100M Inter Hub Bus 10M Inter Hub Bus
MTD658E
100M Inter Hub Bus 10M Inter Hub Bus
MTD658E
100M Inter Hub Bus 10M Inter Hub Bus
MTD658E
100M Inter Hub Bus
RMII0-3
RMII4-7
QUAD PHYsceiver
QUAD PHYsceiver
QUAD Transformer
QUAD Transformer
RJ45
RJ45
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. 2/23 MTD658E Revision 1.1 05/25/2000
MYSON TECHNOLOGY
1.0 PIN CONNECTION (for 8 port mode)
VCC PART3 GND PART2 PART1 PART0 XCOL100 XCOL10 NC NC NC CLK25OUT NC NC GND NC NC NC VCC SYSCLK GND LEDDAT LEDCLK MDC MDIO RSTB 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
MTD658E (8 por t mode)
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CRSDV0 TXD0_1 VCC TXD0_0 TXEN0 RXD0_0 RXD0_1 CRSDV1 TXD1_1 TXD1_0 TXEN1 RXD1_0 RXD1_1 GND CRSDV2 TXD2_1 TXD2_0 TXEN2 RXD2_0 RXD2_1 CRSDV3 TXD3_1 TXD3_0 TXEN3 RXD3_0 RXD3_1 SPD3 SPD2 SPD1 SPD0 VCC GND CRSDV4 TXD4_1 TXD4_0 TXEN4 RXD4_0 RXD4_1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PART4 PART5 PART6 PART7 RXACT0 RXACT1 RXACT2 RXACT3 RXACT4 RXACT5 GND RXACT6 RXACT7 IREQ10_OUT IREQ10_IN0 IREQ10_IN1 IREQ10_IN2 ICOLB10 IACKB10 ICLK10 GND IDAT10 IREQ100_OUT IREQ100_IN0 IREQ100_IN1 IREQ100_IN2 ICOLB100 IACKB100 GND ICLK100 VCC IDAT100_0 IDAT100_1 IDAT100_2 IDAT100_3 IMASTER FD7 UPSWEN
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
MTD658E
SPD4 SPD5 SPD6 SPD7 GND VCC RXD7_1 RXD7_0 TXEN7 TXD7_0 TXD7_1 CRSDV7 RXD6_1 RXD6_0 TXEN6 TXD6_0 TXD6_1 CRSDV6 GND VCC RXD5_1 RXD5_0 TXEN5 TXD5_0 TXD5_1 CRSDV5
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2.0 PIN CONNECTION (for 5 port mode)
VCC PART0 GND NC NC NC XCOL100 XCOL10 NC NC NC CLK25OUT NC NC GND NC NC NC VCC SYSCLK GND LEDDAT LEDCLK MDC MDIO RSTB 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
MTD658E (5 por t mode)
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GND NC VCC NC NC GND GND SPD0 TXD0_3 TXD0_2 NC TXCLK0 GND GND RXCLK0 TXD0_1 TXD0_0 TXEN0 RXD0_0 RXD0_1 GND NC NC NC GND GND RXD0_2 RXD0_3 RXDV0 CRS0 VCC GND CRSDV1 TXD1_1 TXD1_0 TXEN1 RXD1_0 RXD1_1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PART1 PART2 PART3 PART4 NC NC NC RXACT0 RXACT1 RXACT2 GND RXACT3 RXACT4 IREQ10_OUT IREQ10_IN0 IREQ10_IN1 IREQ10_IN2 ICOLB10 IACKB10 ICLK10 GND IDAT10 IREQ100_OUT IREQ100_IN0 IREQ100_IN1 IREQ100_IN2 ICOLB100 IACKB100 GND ICLK100 VCC IDAT100_0 IDAT100_1 IDAT100_2 IDAT100_3 IMASTER FD4 UPSWEN
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
MTD658E
SPD1 SPD2 SPD3 SPD4 GND VCC RXD4_1 RXD4_0 TXEN4 TXD4_0 TXD4_1 CRSDV4 RXD3_1 RXD3_0 TXEN3 TXD3_0 TXD3_1 CRSDV3 GND VCC RXD2_1 RXD2_0 TXEN2 TXD2_0 TXD2_1 CRSDV2
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3.0 PIN DESCRIPTIONS (for 8 port mode)
RMII Port Interface Pins (for 8 port mode) Name CRSDV0 RXD0_0 RXD0_1 TXEN0 TXD0_0 TXD0_1 CRSDV1 RXD1_0 RXD1_1 TXEN1 TXD1_0 TXD1_1 CRSDV2 RXD2_0 RXD2_1 TXEN2 TXD2_0 TXD2_1 CRSDV3 RXD3_0 RXD3_1 TXEN3 TXD3_0 TXD3_1 CRSDV4 RXD4_0 RXD4_1 TXEN4 TXD4_0 TXD4_1 CRSDV5 RXD5_0 RXD5_1 TXEN5 TXD5_0 TXD5_1 Pin Number 1 6 7 5 4 2 8 12 13 11 10 9 15 19 20 18 17 16 21 25 26 24 23 22 33 37 38 36 35 34 39 43 44 42 41 40
MTD658E
I/O Descriptions I Port0 RMII receive interface signal, CRSDV0 is asserted high when port0 media is non_idle. I Port0 RMII receive data bit_0. I O O O I I I O O O I I I O O O I I I O O O I I I O O O I I I O O O Port0 RMII receive data bit_1. Port0 RMII transmit enable signal. Port0 RMII transmit data bit_0. Port0 RMII transmit data bit_1. Port1 RMII receive interface signal, CRSDV1 is asserted high when port1 media is non_idle. Port1 RMII receive data bit_0. Port1 RMII receive data bit_1. Port1 RMII transmit enable signal. Port1 RMII transmit data bit_0. Port1 RMII transmit data bit_1. Port2 RMII receive interface signal, CRSDV2 is asserted high when port2 media is non_idle. Port2 RMII receive data bit_0. Port2 RMII receive data bit_1. Port2 RMII transmit enable signal. Port2 RMII transmit data bit_0. Port2 RMII transmit data bit_1. Port3 RMII receive interface signal, CRSDV3 is asserted high when port3 media is non_idle. Port3 RMII receive data bit_0. Port3 RMII receive data bit_1. Port3 RMII transmit enable signal. Port3 RMII transmit data bit_0. Port3 RMII transmit data bit_1. Port4 MII receive interface signal, CRSDV4 is asserted high when port4 media is non_idle. Port4 RMII receive data bit_0. Port4 RMII receive data bit_1. Port4 RMII transmit enable signal. Port4 RMII transmit data bit_0. Port4 RMII transmit data bit_1. Port5 RMII receive interface signal, CRSDV5 is asserted high when port5 media is non_idle. Port5 RMII receive data bit_0. Port5 RMII receive data bit_1. Port5 RMII transmit enable signal. Port5 RMII transmit data bit_0. Port5 RMII transmit data bit_1.
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RMII Port Interface Pins (for 8 port mode) Name CRSDV6 RXD6_0 RXD6_1 TXEN6 TXD6_0 TXD6_1 CRSDV7 RXD7_0 RXD7_1 TXEN7 TXD7_0 TXD7_1 Pin Number 47 51 52 50 49 48 53 57 58 56 55 54
MTD658E
I/O Descriptions I Port6 RMII receive interface signal, CRSDV6 is asserted high when port6 media is non_idle. I Port6 RMII receive data bit_0. I O O O I I I O O O Port6 RMII receive data bit_1. Port6 RMII transmit enable signal. Port6 RMII transmit data bit_0. Port6 RMII transmit data bit_1. Port7 RMII receive interface signal, CRSDV7 is asserted high when port7 media is non_idle. Port7 RMII receive data bit_0. Port7 RMII receive data bit_1. Port7 RMII transmit enable signal. Port7 RMII transmit data bit_0. Port7 RMII transmit data bit_1.
10M Inter-Bus Interface pins (for 8 port mode) Name IMASTER Pin Number I/O I Descriptions Master hub selection: when high: means hub internal inter_bus arbiter is enabled and hub internal two_port switch is well conneted to 10M_hub core and 100M_hub core . when low: means hub internal inter_bus arbiter is disabled and hub internal two_port switch is not connected to 10M_hub core and 100M_hub core. I/O 10M Inter-Bus port access acknowledge signal (low active). For master hub, this pin is output; for slave hub is input, or while EXT_ARB jumper was set to high, this pin is input from an external arbitration device. I/O 10M Inter-Bus collision signal (low active). For master hub, this pin can output multi hub collision event to inform all slave hub ; for slave hub, this pin is an input, or while EXT_ARB jumper was set to high, this pin is input from an external arbitration device. I 10M Inter-Bus port access request input. I 10M Inter-Bus port access request input. I 10M Inter-Bus port access request input. O 10M Inter-Bus port access request output. I/O 10M Inter-Bus port clock. I/O 10M Inter-Bus port data bit
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IACKB10 84 ICOLB10 85 IREQ10_IN0 IREQ10_IN1 IREQ10_IN2 IREQ10_OUT ICLK10 IDAT10 88 87 86 89 83 81
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100M Inter-Bus Interface pins (for 8 port mode) Name IACKB100 Pin Number 75 ICOLB100 76 IREQ100_IN0 IREQ100_IN1 IREQ100_IN2 IREQ100_OUT ICLK100 IDAT100_0 IDAT100_1 IDAT100_2 IDAT100_3 79 78 77 80 73 71 70 69 68
MTD658E
I/O Descriptions I/O 100M Inter-Bus port access acknowledge signal (low active). For master hub, this pin is output; for slave hub is input, or while EXT_ARB jumper was set to high, this pin is input from an external arbitration device. I/O 100M Inter-Bus collision signal (low active). For master hub, this pin can output multi hub collision event to inform all slave hub ; for slave hub, this pin is an input, or while EXT_ARB jumper was set to high, this pin is input from an external arbitration device. I 100M Inter-Bus port access request input. I 100M Inter-Bus port access request input. I 100M Inter-Bus port access request input. O 100M Inter-Bus port access request output. I/O 100M Inter-Bus port clock. I/O 100M Inter-Bus port data bit 0. I/O 100M Inter-Bus port data bit 1. I/O 100M Inter-Bus port data bit 2. I/O 100M Inter-Bus port data bit 3. LED Interface Pins (for 8 port mode)
Name RXACT7-0 PART7-0
Pin Number 90,91,93,94, 95,96,97,98 99,100,101, 102,104,106, 107,108
I/O I/O I/O
Descriptions Port 7-0 Rx Activity LED Outputs, low_active. Direct output per port receive activity status for LED display. Port 7-0 Partition LED Outputs, low_active. Direct output per port partition status for LED display. During power on reset PART7 pin use as MII setting start PHY device ID selection. 4.7K pull up resistor will set PHY device ID from 5h08 - 5h0f, no pull up 4.7k resistor will set PHY device ID from 5h04 -5h0b. 100M Hub Collision LED Output, low_active. 10M Hub Collision LED Output, low_active.
XCOL100 XCOL10
109 110
I/O I/O
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LED Interface Pins (for 8 port mode) Name LEDDAT Pin Number I/O I/O
MTD658E
Descriptions LED display serial data out, high_active; mapping for LEDCLK signal' burst clock , its serial out data sequence is : ( first bit be shifted out s is from b00, and end of burst bit is b23) b00: port0 partition b01: port1 partition b08: 10hub_col b09: 100hub_col b10: asram_test_fail b11: port3 partition b12: port4 partition b13: port5 partition b14: port6 partition b16: port0 rx_activity b17: port1 rx_activity b18: port2 rx_activity b19: port3 rx_activity b20: port4 rx_activity b21: port5 rx_activity b22: port6 rx_activity
124
b02: port2 partition b03: port3 partition b04: port4 partition b05: port5 partition b06: port6 partition
LEDCLK 125
I/O
b07: port7 partition b15: port7 partition b23: port7 rx_activity LED display clock signal; the signal is a discontinued clock for LED data serial shift out. Every clock burst have 24 cycles ( period : 160 ns), and the clock burst will be repeated with every 42ms.
Miscellaneous Pins (for 8 port mode) Name RSTB SYSCLK CLK25MOUT MDC MDIO UPSWEN Pin Number 128 122 114 126 127 65 FD7 66 SPD0 SPD1 SPD2 SPD3 SPD4 SPD5 SPD6 30 29 28 27 64 63 62 I I I I I I I I I/O I I I/O I/O I/O I Descriptions System reset input, low active. 50MHz system clock input. 25MHz clock output. MII management clock inout. MII management data inout. Up_link switch port enabling : one of internal two_port switch port will connect to 100M_hub domain, and another port will redirect to RMII port7. When up_link switch port enabling, this pin is port7' full_deplex indis cator, input from PHY. When hign , indicate port7 in running on full_duplex mode. When low, indicate on half_duplex mode. Port0 speed indicator, input from PHY. SPD0 input low: 100M , input high: 10M. Port1 speed indicator, input from PHY. SPD1 input low: 100M , input high: 10M. Port2 speed indicator, input from PHY. SPD2 input low: 100M , input high: 10M. Port3 speed indicator, input from PHY. SPD3 input low: 100M , input high: 10M. Port4 speed indicator, input from PHY. SPD4 input low: 100M , input high: 10M. Port5 speed indicator, input from PHY. SPD5 input low: 100M , input high: 10M. Port6 speed indicator, input from PHY. SPD6 input low: 100M , input high: 10M.
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Miscellaneous Pins (for 8 port mode) Name SPD7 VCC GND Pin Number 61 I/O Descriptions I Port7 speed indicator, input from PHY.
MTD658E
SPD7 input low: 100M , input high: 10M. 3,31,45,59, PWR Power pins 72,103,121 14,32,46,60, GND Ground pins 74,82,92,105 ,117,123 111,112,113, NC No connection pins 115,116,118, 119,120
NC_pin
Power On Configuration Set Up Table (for 8 port mode) Name TXEN2 Pin Number 18 TXEN5 42 I/O Descriptions I/O Back_pressure disable : ( power on external jumper configuration ) - external pull_low (default ) : normal mode (back_pressure enbale) - external pull_high: back_pressure disable I/O Auto MII_setting bypass : ( power on external jumper configuration ) - external pull_low (default ) : normal mode ( auto MII_setting); after power_on, MTD658E will auto setup PHY devices be forced in half_ duplex mode for repeater apllication. PART7 99 - external pull_high: auto MII_setting bypass I/O PHY_ID 5h8 starting enable :(power on external jumper configuration) - external pull_low (default ) : MII setting PHY_ID start address from 5h04 to 5h0b. - external pull_high: MII setting PHY_ID start address from MDC 126 5h08 to 5h0f. I/O 1522 bytes packet accept enable : ( power on external jumper configuration ) - external pull_low (default ) : normal mode ( <=1518 bytes packet accept) I/O 124 - external pull_high: <= 1522 bytes packet accept External arbiter enable : ( power on external jumper configuration ) - external pull_low (default ) : normal mode (inter_repeater bus use internal arbiter) - external pull_high: inter_repeater bus use external arbiter .
LEDDAT
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4.0 PIN DESCRIPTIONS (for 5 port mode)
MII Port (port0) Interface Pins (for 5 port mode) Name RXD0_0 RXD0_1 RXD0_2 RXD0_3 CRS0 RXDV0 RXCLK0 TXEN0 TXD0_0 TXD0_1 TXD0_2 TXD0_3 TXCLK0 Pin Number 19 20 27 28 30 29 15 18 17 16 10 9 12 I/O Descriptions I Port0 MII receive data bit_0. I I I I I I O O O O O I Port0 MII receive data bit_1. Port0 MII receive data bit_2.
MTD658E
Port0 MII receive data bit_3. Port0 MII asynchronous carrier indicator from PHY device. Port0 MII synchronous receive data valid signal from PHY device. Port0 MII receive clock. Port0 MII transmit enable signal. Port0 MII transmit data bit_0. Port0 MII transmit data bit_1. Port0 MII transmit data bit_2. Port0 MII transmit data bit_3. Port0 MII transmit clock.
RMII Port (port1~port4) Interface Pins (for 5 port mode) Name CRSDV1 RXD1_0 RXD1_1 TXEN1 TXD1_0 TXD1_1 CRSDV2 RXD2_0 RXD2_1 TXEN2 TXD2_0 TXD2_1 CRSDV3 RXD3_0 RXD3_1 TXEN3 TXD3_0 TXD3_1 CRSDV4 Pin Number 33 37 38 36 35 34 39 43 44 42 41 40 47 51 52 50 49 48 53 I/O Descriptions I Port1 RMII receive interface signal, CRSDV1 is asserted high when I I O O O I I I O O O I I I O O O I port1 media is non_idle. Port1 RMII receive data bit_0. Port1 RMII receive data bit_1. Port1 RMII transmit enable signal. Port1 RMII transmit data bit_0. Port1 RMII transmit data bit_1. Port2 RMII receive interface signal, CRSDV2 is asserted high when port2 media is non_idle. Port2 RMII receive data bit_0. Port2 RMII receive data bit_1. Port2 RMII transmit enable signal. Port2 RMII transmit data bit_0. Port2 RMII transmit data bit_1. Port3 RMII receive interface signal, CRSDV3 is asserted high when port3 media is non_idle. Port3 RMII receive data bit_0. Port3 RMII receive data bit_1. Port3 RMII transmit enable signal. Port3 RMII transmit data bit_0. Port3 RMII transmit data bit_1. Port4 RMII receive interface signal, CRSDV4 is asserted high when port4 media is non_idle.
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Name RXD4_0 RXD4_1 TXEN4 TXD4_0 TXD4_1 Pin Number 57 58 56 55 54 I/O Descriptions I Port4 RMII receive data bit_0. I O O O Port4 RMII receive data bit_1. Port4 RMII transmit enable signal. Port4 RMII transmit data bit_0. Port4 RMII transmit data bit_1.
MTD658E
RMII Port (port1~port4) Interface Pins (for 5 port mode)
10M Inter-Bus Interface pins (for 5 port mode) Name IMASTER Pin Number I/O I Descriptions Master hub selection: when high: means hub internal inter_bus arbiter is enabled and hub internal two_port switch is well conneted to 10M_hub core and 100M_hub core . when low: means hub internal inter_bus arbiter is disabled and hub internal two_port switch is not connected to 10M_hub core and 100M_hub core. 10M Inter-Bus port access acknowledge signal (low active). For master hub, this pin is output; for slave hub is input, or while EXT_ARB jumper was set to high, this pin is input from an external arbitration device. 10M Inter-Bus collision signal (low active). For master hub, this pin can output multi hub collision event to inform all slave hub ; for slave hub, this pin is an input, or while EXT_ARB jumper was set to high, this pin is input from an external arbitration device. 10M Inter-Bus port access request input. 10M Inter-Bus port access request input. 10M Inter-Bus port access request input. 10M Inter-Bus port access request output. 10M Inter-Bus port clock. 10M Inter-Bus port data bit
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IACKB10 84 ICOLB10 85 IREQ10_IN0 IREQ10_IN1 IREQ10_IN2 IREQ10_OUT ICLK10 IDAT10 Name IACKB100 88 87 86 89 83 81 Pin Number 75 ICOLB100 76 IREQ100_IN0 IREQ100_IN1 IREQ100_IN2 IREQ100_OUT 79 78 77 80
I/O
I/O
I I I O I/O I/O
100M Inter-Bus Interface pins (for 5 port mode) I/O Descriptions I/O 100M Inter-Bus port access acknowledge signal (low active). For master hub, this pin is output; for slave hub is input, or while EXT_ARB jumper was set to high, this pin is input from an external arbitration device. I/O 100M Inter-Bus collision signal (low active). For master hub, this pin can output multi hub collision event to inform all slave hub ; for slave hub, this pin is an input, or while EXT_ARB jumper was set to high, this pin is input from an external arbitration device. I 100M Inter-Bus port access request input. I 100M Inter-Bus port access request input. I 100M Inter-Bus port access request input. O 100M Inter-Bus port access request output.
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100M Inter-Bus Interface pins (for 5 port mode) Name ICLK100 IDAT100_0 IDAT100_1 IDAT100_2 IDAT100_3 Pin Number 73 71 70 69 68 I/O I/O I/O I/O I/O I/O Descriptions 100M Inter-Bus port clock. 100M Inter-Bus port data bit 0. 100M Inter-Bus port data bit 1. 100M Inter-Bus port data bit 2. 100M Inter-Bus port data bit 3.
MTD658E
LED Interface Pins (for 5 port mode) Name RXACT4-0 PART4-0 99,100,101, 102,104 XCOL100 XCOL10 LEDDAT 109 110 I/O I/O I/O Pin Number 90,91,93,94, 95 I/O I/O I/O Descriptions Port 4-0 Rx Activity LED Outputs, low_active. Direct output per port receive activity status for LED display. Port 4-0 Partition LED Outputs, low_active. Direct output per port partition status for LED display. During power on reset PART4 pin use as MII setting start PHY device ID selection. 4.7K pull up resistor will set PHY device ID from 5h08 - 5h0f, no pull up 4.7k resistor will set PHY device ID from 5h04 -5h0b. 100M Hub Collision LED Output, low_active. 10M Hub Collision LED Output, low_active. LED display serial data out, high_active; mapping for LEDCLK signal' burst clock , its serial out data sequence is : ( first bit be shifted out s is from b00, and end of burst bit is b23) b00: *********** b01: ********** b02: ********** 124 b03: port0 partition b04: port1 partition b05: port2 partition b06: port3 partition b07: port4 partition LEDCLK 125 I/O b08: 10hub_col b09: 100hub_col b10: asram_test_fail b11: port0 partition b12: port1 partition b13: port2 partition b14: port3 partition b15: port4 partition b16: ************ b17: ************ b18: ************ b19: port0 rx_activity b20: port1 rx_activity b21: port2 rx_activity b22: port3 rx_activity b23: port4 rx_activity
LED display clock signal, the signal is a discontinued clock for LED data serial shift out. Every clock burst have 24 cycles ( period : 160 ns), and the clock burst will be repeated with every 42ms.
Miscellaneous Pins (for 5 port mode) Name RSTB SYSCLK CLK25MOUT MDC MDIO Pin Number 128 122 114 126 127 I/O I I I/O I/O I/O Descriptions System reset input, low active. 50MHz system clock input 25MHz clock output. MII management clock inout MII management data inout
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Miscellaneous Pins (for 5 port mode) Name UPSWEN Pin Number 65 FD4 66 SPD0 SPD1 SPD2 SPD3 SPD4 NC_pin 8 64 63 62 61 2,4,5,11,22, 23,24,96,97, 98,106,107, 108,111,112, 113,115,116, 118,119,120 3,31,45,59, PWR Power pins 72,103,121 1,6,7,13,14, GND Ground pins 21,25,26,32, 46,60,74,82, 92,105,117, 123
MTD658E
I/O Descriptions I Up_link switch port enabling : one of internal two_port switch port will connect to 100M_hub domain, and another port will redirect to RMII port4. I When up_link switch port enabling, this pin is port4' full_deplex indis cator, input from PHY. When hign , indicate port4 in running on full_duplex mode. When low, indicate on half_duplex mode. I Port0 speed indicator, input from PHY. I I I I SPD0 input low: 100M , input high: 10M. Port1 speed indicator, input from PHY. SPD1 input low: 100M , input high: 10M. Port2 speed indicator, input from PHY. SPD2 input low: 100M , input high: 10M. Port3 speed indicator, input from PHY. SPD3 input low: 100M , input high: 10M. Port4 speed indicator, input from PHY.
SPD4 input low: 100M , input high: 10M. NC No connection pins
VCC GND
Power On Configuration Set Up Table (for 5 port mode) Name NC_11 Pin Number I/O Descriptions I/O Port0 MII interface enable : ( power on external jumper configuration ) - pin floating : Port0 MII interface disable (Port0 : be configured in 11 RMII interface) - external pull_high: Port0 MII interface enable. (suitable for 5 port dual TXEN0 18 speed hub application). I/O Back_pressure disable : ( power on external jumper configuration ) - external pull_low (default ) : normal mode (back_pressure enbale) - external pull_high: back_pressure disable
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Name TXEN2 Pin Number
MTD658E
Power On Configuration Set Up Table (for 5 port mode) I/O Descriptions I/O Auto MII_setting bypass : ( power on external jumper configuration ) - external pull_low (default ) : normal mode ( auto MII_setting); after 42 power_on, MTD658E will auto setup PHY devices be forced in half_ duplex mode for repeater apllication. PART4 99 - external pull_high: auto MII_setting bypass. I/O PHY_ID 5h0b starting enable :(power on external jumper configuration) - external pull_low (default ) : MII setting PHY_ID start address from 5h07 to 5h0b. - external pull_high: MII setting PHY_ID start address from MDC 126 I/O 5h0b to 5h0f. 1522 bytes packet accept enable : ( power on external jumper configuration ) - external pull_low (default ) : normal mode ( <=1518 bytes packet accept) I/O 124 - external pull_high: <= 1522 bytes packet accept External arbiter enable : ( power on external jumper configuration ) - external pull_low (default ) : normal mode (inter_repeater bus use internal arbiter) - external pull_high: inter_repeater bus use external arbiter .
LEDDAT
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5.0 FUNCTIONAL DESCRIPTIONS
MTD658E
The MTD658E is conformed to IEEE802.3 chapter 9 and IEEE802.3u clause 27 specifications. The MTD658E provides 8 Reduced MII interfaces and an embedded two port switch (build_in 64k8 ASRAM on chip) to construct a 10M/100M dual speed Hub application. And also, MTD658E can be configured to 5 port mode, it will provide 4 RMII and 1 MII interface. Two Inter-Bus are also provided for stackable 10M/100M dual speed Hub application. Since MTD658E build_in memory on chip, there are no need any extra memorys in the application board.The MTD658E functions are described as follows:
5.1 Repeatation and data handling
8 independent RMII ports integrated with IEEE802.3 chapter 9 and IEEE802.3u clause 27 repeater functions simultaneously. MTD658E embedded two Hub cores (10M and 100M) ,and each dedicated RMII interface port can get per port' speed information from per port speed input pin, and then s MTD658E will switch individual port to their appropriated Hub core functions (10M or 100M). The MTD658E receive packets from each RMII ports, and redirect port' input packet to 10M or 100M s Hub core according each port' speed. The internal IEEE802.3 chapter 9 or IEEE802.3u clause 27 s repeater main state machine will starts to repeat the input packet to all ports except the input port. If larger than or equal to two ports have input packet simultaneously, this will be treated as a collision, and MTD658E will assert an arbitrary JAM pattern to all ports'output until collision event disappear and network is idle.
5.2 Partition
The MTD658E provides 10M/100M auto partition/reconnection functions to guarantee the network segment performance by means of dectecting a consecutive collisions. Each dedicated RMII port has implement a individual 10M/100M auto partition/reconnection state machine. If port' consecutive collis sion number over or equal to CClimit (10M CClimit default is 32, 100M CClimit default is 64), this port will be partitioned. Reconnection will occurs after a larger than 512 bit time packet was received or transmitted from this partitioned port without any collision. When port is under partition state, MTD658E will not accept any input messages from this port (just monitor input message), but will continue output repeated messages to this partition port. Some new partition criterions are also implement, such as long_collision_partition event, jabber_partition event. In 10M/100M partition state machine, longer than 1024 bit time continueous collision will force port enter partition state. In 100M partition state machine, if port enter jabber_on state, this port will be partitioned. In 10M, jabber_partition function is not implemented.
5.3 Jabber
The jabber protect function is used to prevent an illegally long packet reception. After the MTD658E received a longer than 65536 +/- 6.25% bit times packet, this receive port` receive/transmit path will be s inhibited until carrier is no longer detected.
5.4 MII Setting
Due to HUB is an half duplex device, the MTD658E need to force all connected phsical devices to work in half duplex environment. The MTD658E will setting all PHY' SMI register 4' half/full duplex bit durs s ing power on, and than restart auto-negotiation procedure to work in half duplex mode. In 8 port mode, the PHY' device ID should be setted from 5h04 - 5h0b (port0-7) or from 5h08 -5h0f (port0-7); In 5 port s mode, the PHY device ID should be setted from 5h07 - 5h0b (port0-4) or from 5h0b -5h0f (port0-4).
5.5 Inter-Bus Interface
Two Inter-Bus Interface are provided by the MTD658E, One is 10M Inter-Bus Interface, the other is 100M Inter-Bus Interface. The Inter-Bus interface is designed for stackable hub application. For each domain, up to 4 MTD658Es can be stacked through this Inter-Bus without any external arbitration logic. The Inter-Bus Interface includes IMASTER, IDATA (100M: use IDAT<3:0>, 10M: use only IDAT), REQOUT, REQIN0-2, ICLK, IACKB, ICOLB pins. IMASTER decide which MTD658E can arbitrate the Inter-Bus, and only one MTD658E' IMASTER can be tie high in a stackable Hub. IDATA are synchros
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MTD658E
nous with ICLK. The MTD658E output REQOUT to inform Inter-Bus Interface that it need the Inter-Bus right. When IACKB is asserted by Inter-Bus master after REQOUT asserted, the MTD658E which asserted REQOUT will get the bus right and put the transmit data into IDATA. If the MTD658E did not assert REQOUT , but IACKB is asserted, means this MTD658E can get data from IDATA bus. When only one MTD658E output REQOUT to Inter-Bus Interface, IACKB will be asserted by Inter-Bus master device, If larger than two MTD658E' REQOUT were asserted, Inter-Bus master will not assert IACKB , s but will assert ICOLB to inform all the connected MTD658Es. The Inter-Bus interface can also be programmed to EXT_ARB mode, using LEDDAT pin' jumper sets ting. In this mode, Inter-Bus interface need an external arbitration logic to arbitrate Inter-Bus operation. And in this mode, the stackable capability is not limitted by the MTD658E' REQIN pins number. s
5.6 10M/100M packet Switch
The MTD658E inplements a 10/100M two port switch for 10M/100M packet switching. Total 2K address entrys are provided for packets'SA learning and DA routing; and alsoprovide automatic aging function ( aging time = 300secs). The input packet from 10MHub ( or 100M Hub) will be stored to external memory first, while packet is good for forward ( CRC chech ok, length = 64Bytes ~ 1518Bytes or 1522 Bytes, and not local packets ) , than forward this packet to 100M Hub (or 10M Hub).
5.7 Uplink Switch Port
The MTD658E can config one switch port as an uplink switch port. When UPSWEN pin is high, and IMASTER pin is low, one of the intenal switch port is connect to 100M Hub, the other is connected to RMII the highest port . In uplink switch mode, the highest port can operate in 10M/100M (in 8 port mode : from SPD7 pin; in 5 port mode: from SPD4 pin ), and operate in half/full duplex (in 8 port mode: from FD7 pin; in 5 port mode: from FD4 pin).
5.8 Memory Interface
The MTD658E build-in an asynchronous SRAM as two port switchs'packet buffers, total has 64K byte embedded memory for packet buffering.
5.9 MII management
The MTD658E can be managed through MDC, MDIO pins. The MTD658E implements 3 MII registers for function control and status report (see Section 4.0 on page ). The management frame format is compliant to IEEE802.3u clause 22, and the device ID is fixed to 5' internally. h1f
5.10 LED display
The MTD658E implements three display modes, port RX activity, 10/100M domain collision, port partition. The LED data pin LEDDAT is high actived. One strobe pin LEDCLK(24 burst clock/per 42ms) is used to latch serial LEDDAT information, and user can shift the latched data into byte aligned shift register to drive LEDs. The MTD658E also provide status pins to direct output per port' receive activity/partition, 100M Hub s collision, 10M Hub collision, embedded ASRM memory test fail status.
6.0 Registers
The MTD658E implements 3 MII registers, define as following tables: TABLE 1. MII r egister s REG NO 0 Bits 0 1 Name CtlReg0 DisPar10 R/W R/W Descriptions CONTROL REGISTER 0 Reserved. Set this bit will disable 10M hub core partition function.
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TABLE 1. MII r egister s REG NO Bits Name R/W Descriptions
MTD658E
Default
1
2 3 4
2 DisPar100 Set this bit will disable 100M hub core partition function. 1b0 3 DisJab10 Set this bit will disable 10M hub core Jabber function. 1b0 4 DisJab100 Set this bit will disable 100M hub core Jabber function. 1b0 5-8 Reserved 4b000 9 CClimit100 Set high will program 100M partition cclimit to 128. 1b0(64) 10 CClimit10 Set high will program 10M partition cclimit to 64. 1b0(32) 11-15 Reserved 2b00 CtlReg1 R/W CONTROL REGISTER 1 16h0000 0-7 DisPort Set bits high disable port 0-7 RMII ports. 8h000 8-15 Reserved. Reserved Reserved AgeReg R/W AGE REGISTER 16h12c Change this register' content will change Aging Time s 0-15 AgeTime value(Unit:Sec)
"R/W" means read/writable.
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7.0 Electrical Characteristics
7.1 Absolute Maximum Ratings
Symbol Parameter VCC Power Supply Voltage VIN VOUT TSTG Input Voltage Output Voltage Storage Temperature RATING -0.3 to 3.6 -0.3 to Vcc+0.3 -0.3 to Vcc+0.3 -55 to 150
MTD658E
Unit V V V
o
C
7.2 Recommended Operating Conditions
Symbol Parameter VCC Commercial Power Supply Voltage VIN Input Voltage TOPR Commercial Junction Operating Temperature Industrial Junction Operating Temperature Min. 3.0 0 0 -40 Typ. 3.3 25 25 Max. 3.6 Vcc 115 125 Unit V V
o o
C C
7.3 DC Electrical Characteristics
Symbol Parameter IIL Input Leakage Current IOZ Tri-state Leakage Current CIN COUT CBID3 VIL VIH VOH VOL RI Input Capacitance Output Capacitance Bi-direction buffer Capacitance Input Low Voltage Input High Voltage Output High Voltage Output Low Voltage Input Pull-up/down resistance CMOS CMOS 0.7*Vcc IOL=2,4,8,12,16,24mA 2.4 IOH=2,4,8,12,16,24mA VIL=0V or VIH=VCC 75 0.4 2.7 2.7 Conditions no pull-up or down Min. -1 -10 2.8 4.9 4.9 0.3*Vcc Typ. Max. 1 10 Unit uA uA pF pF pF V V V V KOhm
(Under recommended operating conditions and Vcc = 3.0 ~ 3.6V, Tj = 0 to +115 oC)
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7.4 Electrical Characteristics
FIGURE 1. MII timing RXCLK0 CRS0/RXDV0 RXD0[3:0] TXCLK0 T7 TXEN0 TXD0[3:0] T8 Valid T5 T6 Valid
MTD658E
Symbol T5 T6 T7 T8
Parameter MII input setup time MII input hold time MII output setup time MII output hold time
Min. 10 10 3 5
Typ.
Max.
Unit nS nS nS nS
Note
FIGURE 2. RMII timing REFCLK CRSDV RXD[1:0] TXEN TXD[1:0] T1 T2 Valid T3 T4 Valid
Symbol T1 T2 T3 T4
Parameter RMII input setup time RMII input hold time RMII output setup time RMII output hold time
Min. 1 1 3 5
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Typ.
Max.
Unit nS nS nS nS
Note
MTD658E Revision 1.1 05/25/2000
MYSON TECHNOLOGY
FIGURE 3. Inter -Bus Inter face timing I ICLK100, ICLK10 IDATA100, IDAT10 T13 T14 Valid
MTD658E
Symbol Parameter T13 Inter-Bus output setup time(100M) Inter-Bus output setup time(10M) T14 Inter-Bus output hold time(100M) Inter-Bus output hold time(10M)
Min. 15 20
Typ. 50
Max. 20 25
50
Unit nS nS nS nS
Note
FIGURE 4. Inter -Bus Inter face timing II IMASTER REQOUT100, REQOUT10 REQIN100, REQIN10 IACKB100, IACKB10 ICOLB100, ICOLB10 T15 T16 T18 T17
Symbol T15 T16
T17
T18
Parameter Inter-Bus master REQOUT asserted to IACKB asserted propogation delay Inter-Bus master REQOUT deasserted to IACKB deasserted propogation delay Inter-Bus master REQIN asserted to IACKB deasserted(ICOLB asserted) propogation delay(SOJ) Inter-Bus master REQOUT deasserted to IACKB asserted(ICOLBdeasserted) propogation delay(EOJ)
Min. 7 0
Typ.
Max. 20
Unit nS nS
Note 1 1
1
5
5
17
nS
1
0
1
5
nS
1
Note 1 : In 10M/100M Inter-Bus interface, T15-T18 have the same value.
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FIGURE 5. Inter -Bus Inter face timing III IMASTER REQOUT100, REQOUT10 REQIN100, REQIN10 IACKB100, IACKB10 ICOLB100, ICOLB10 T19 T20 T22 T21
MTD658E
Symbol T19 T20
T21
T22
Parameter Inter-Bus slave REQOUT asserted to IACKB asserted propogation delay Inter-Bus slave REQOUT deasserted to IACKB deasserted propogation delay Inter-Bus slave REQIN asserted to IACKB deasserted(ICOLB asserted) propogation delay(SOJ) Inter-Bus slave REQOUT deasserted to IACKB asserted(ICOLBdeasserted) propogation delay(EOJ)
Min. 5 5
Typ.
Max. 20 20
Unit nS nS
Note 2 2
5
20
nS
2
5
20
nS
2
Note 2 : In 10M/100M Inter-Bus interface, T19-T22 have the same value. FIGURE 6. MII Management timing Input Timing MDC MDIO T24 T25 Valid Output Timing MDC MDIO T26 T27 Valid T23
Symbol Parameter T23 MDC clock cycle T23 MDIO input setup time
Min. 10
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Typ. 400
Max.
Unit nS nS
Note
MTD658E Revision 1.1 05/25/2000
MYSON TECHNOLOGY
Symbol Parameter T25 MDIO input hold time T26 MDIO output setup time T27 MDIO output hold time Min. 10 182 206 Typ. Max. 194 218
MTD658E
Unit nS nS nS Note
FIGURE 7. LED output timing T29 T28 LEDCLK .... T30 LEDCLK T31 LEDDAT T33 RXACT7-0, XCOL100, XCOL10 T32 ....
Symbol T28 T29 T30 T31 T32 T33
Parameter 24 LED burst clocks duration LED burst clock cycle time LED burst clock cycle LEDDAT to LEDCLK setup time LEDDAT to LEDCLK setup time LED Output flash rate
Min.
Typ. 3.84 42 160 80 80 42
Max.
Unit uS mS nS nS nS mS
Note
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8.0 128 pin PQFP Package Data
MTD658E
D1 D 102 103 65 64
Symbol A A1 A2 B C D D1
E1
Dimension in inch Min 0.010 Norm Max 0.134 0.117
Dimension in mm Min 0.25 2.73 0.17 0.09 Norm 2.85 0.22 Max 3.40 2.97 0.27 0.20
0.107 0.112
0.007 0.009 0.011 0.004 0.008
0.906 0.913 0.921 23.00 23.20 23.40 0.783 0.787 0.791 19.90 20.00 20.10 0.669 0.677 0.685 17.00 17.20 17.40 0.547 0.551 0.555 13.90 14.00 14.10 0.020 BSC 0.029 0.035 0.041 0.063 BSC 0o 0.004 7o 0o 0.73 0.50 BSC 0.88 1.60 BSC 0.10 7o 1.03
E
E
E1 e L
128 1 e B 38
39
L1 y z
See Detail B See Detail A Seating Plane
A1
y
Note: 1.Dimension D1 & E1 do not include mold protrusion. But mold mismatch is included. Allowable protrusion is .25mm/.010" per side. 2.Dimension B does not include dambar protrusion. Allowable dambar protrusion .08mm/.003". Total in excess of the B dimemsion at maximum material condition. Dambar cannot be located on the lower radius or the foot. 3.Controlling dimension : Millimeter.
A2
A
B
With Plating Gage Plane L z Base Metal L1 Detail A Detail B
C
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